Kurt Sprague's Technical Portfolio
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Mini CPU
ECEN2350 Digital Logic - Project 1
Group Members: Kurt Sprague and Andrew Zhu
We programmed the DE10-Lite FPGA in the HDL Verilog to create a very basic CPU. This CPU could do basic arithmetic: add and subtract in hex with a range from 0 to F, and multiply or divide by 2 with a hex range of FF to 00. The CPU can also do 4 bit logic AND, OR, XOR, and 8 bit logic NOT. Lastly, the CPU can do comparison between two 4 bit numbers (greater than, less than, equal to, or max). The modes are controlled by two buttons, while the functions are controlled by two switches.
Block Diagrams of Smaller Modules
In the gallery there are block diagrams for the three levels of block diagrams we have. Small, medium, and large represented by exor.v, logical.v, and mux.v
Top File Block Diagram
Here is a block diagram from the top level of the hierarchical design. If you would like to view a larger version, click on the photo.
Multiplexer Truth Table
The multiplexer is the control center of this project, so above I included the truth table. To keep things simple, refer to the following key.
KEY[0] is Button 1
KEY[1] is Button 2
SW[9] is Switch 1
SW[8] is Switch 2
Functionality
Arithmetic: Button 1 = 0 Button 2 = 0
Switch 1 = 0 Switch 2 = 0 ADD (AA)
Switch 1 = 0 Switch 2 = 1 SUBTRACT (A5)
Switch 1 = 1 Switch 2 = 0 X2 (AP)
Switch 1 = 1 Switch 2 = 1 /2 (Ad)
Bitwise Logical: Button 1 = 0 Button 2 = 1
Switch 1 = 0 Switch 2 = 0 AND (LA)
Switch 1 = 0 Switch 2 = 1 OR (L0)
Switch 1 = 1 Switch 2 = 0 XOR (LH)
Switch 1 = 1 Switch 2 = 1 NOT (Ln)
Comparison: Button 1 = 1 Button 2 = 0
Switch 1 = 0 Switch 2 = 0 EQUAL (CE)
Switch 1 = 0 Switch 2 = 1 GREATER (C6)
Switch 1 = 1 Switch 2 = 0 LESS (CL)
Switch 1 = 1 Switch 2 = 1 MAX (CH)
A Difficult Truth Table
For the max function in the comparison module, there would initially be a 256 line truth table, but you can reduce the truth table to only 2 lines by utilizing the greater than module we made. The simplified truth tables are shown to the left.
Something Extra
To truly master the clock, we programmed the FPGAÂ to make a Knight Rider tribute.
More Extras
Multi-Mode Knight Rider
Signed Adder and Subtractor
We decided to dedicate another section to signed adding and subtracting.Â
For the signed adder (SA) we have 8 + 4 = FC
For the signed subtractor we have 4 - 8 = FC
FC is signed -4 proving the subtractor works, and also showing that the signed adder has a limit of adding up to 7
We had to add 2 extra lines to the multiplexer truth table, so we could switch into these functions.
Closing Remarks
This small CPU was basically a crash course or trial by fire into the world of Verilog. There are examples of both procedural and behavioral implementations throughout the code. This project also taught me quite a bit about wires, registers, and how bits are represented/transferred. The most difficult part of this project was translating the block diagrams to actual Verilog code. Coming from a C/C++ background the syntax was a tricky to figure out, and I found myself spending most of my time debugging syntax. I would say in the future/next time I want to implement the Arduino UNO port on the FPGA.