Kurt Sprague's Technical Portfolio
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Reaction Timer
ECEN 2350 Digital Logic: Project 2
Group Members: Kurt Sprague and Andrew Zhu
We programmed the FPGA, DE10-Lite, in the HDL Verilog to display a reaction timer. The user presses an enable button, then waits until an LED turns on. In order to make the test accurate, we used a Linear-Feedback Shift Register (LFSR) to "randomly" generate a time. After the LED turns on, a counter in milliseconds will be counting up, and is shown on the seven segment displays. After the user presses the stop button, the timer stops, and if it is the fastest time it is stored as a high score. The timer then can be reset, and the user can try again.
Block Diagram
State Machine Diagram
A Random Number Generator Using Hardware?
Correct! Or rather pseudo-random, as there is nothing truly random when it comes to hardware. The LFSR we used is similar to using rand() in C++ with a seed dependent on time. Our LFSR triggers on the positive edge of the FPGA's 50 MHz clock. Continuing the comparison to rand(), we need a seed in order for this to truly be random. In an LFSR, the seed is the feedback. In our design the feedback will take in 2 bits from a buffer shift register, put them through an EXNOR gate, and feed the result back into the same buffer shift register. This process is constantly going, and only stops once the enable button is pressed. Once stopped, the buffer shift register will represent a number between 0-255. A clock then counts up to this number, and when it reaches it the LED turns on. We surveyed 10 people's reaction times, and placed them in the histogram to the left. The the uneven distribution is from the relatively small sample size, but does show a difference across the 10 tested.
Clock divider
The clock on the DE10-Lite is 50 MHz. That is far too fast to count someone's reaction time in milliseconds, so we had to step it down. By implementing a module that output a clock cycle for every 25000 received.
The central hub
Our state machine module was the brain of this reaction timer. It had 4 states that were designated by bits from 0 to 3. The state machine was a Moore Machine, that took in 2 buttons and 2 switches. Through its 4 states, it controlled the whole project.
Lighter and BCDcounter
The lighter module will light the LED, after given the go from the LFSR. The lighter module will then send an enable signal to our BCD counter. The counter goes from 0-9 from each hex, and stops when the user presses the stop button.
Highscore
The output of BCDcounter is immediately analyzed when the stop button is pressed. If the value is lower than any previous value, it will be stored in a register, until a signal is given from the state machine to change the display from idle to the high score.
BCD decoder
This module was a single module for decoding BCD and it output the bits needed to display numbers on the seven segment display. We reused this module for every display.
Demo
Minor correction: When I say milliseconds, I mean deciseconds as the two most right digits are in milliseconds.
Demo Extra
Conclusion
Our reaction timer setup had a couple of difficulties to overcome. The first being the BCD to count 1 at a time once the previous one had reached 9. The second hardest part was to make a random number generator in Verilog. The answer to these two problems was in the end to make it as simple as possible. We found that when we made our LFSR have only one gate on the feedback, it was much easier to code. Similarly, when we made the BCD more of a standalone module, it was much easier to implement. After completing this project, I now feel as if I have a better understanding of clocks and shift registers, as we had to use that technology frequently.